The increasing capabilities of integrated circuits and the complexity of applications have led hardware design methods and tools to higher levels of abstraction and high-level synthesis is one of the key steps in increasing the level of abstraction. In recent years, ext
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The increasing capabilities of integrated circuits and the complexity of applications have led hardware design methods and tools to higher levels of abstraction and high-level synthesis is one of the key steps in increasing the level of abstraction. In recent years, extensive research has been conducted on the design of decimal arithmetic reconfigurable architectures. Since, on the one hand, the effective use of these architectures depends on the existence of appropriate algorithms and tools to implement the design on the hardware, and on the other hand, research on the development of these algorithms has been very limited, this paper will present methods for the automated synthesis of decimal arithmetic circuits on a coarse-grained reconfigurable architecture. The platform chosen to execute the proposed algorithms is the DARA coarse-grained reconfigurable architecture, which is optimized for decimal arithmetic. The algorithms proposed for resource allocation of synthesis include a heuristic method and an ILP algorithm. The results show that, as expected, for the limited architectural dimensions used, the ILP algorithm performs significantly (about 30%) better than the heuristic algorithm.
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